libpostproc.hg: postprocess_template.c comparison

comparison postprocess_template.c @ 113:bf8f52662dc3 libpostproc

Replace long with x86_reg in postprocess_template.c like in all other x86 assembler code files, just libpostprocess was forgotten.

author	reimar
date	Sun, 02 Nov 2008 18:59:44 +0000
parents	d4d919ebc31c
children	bdd1788fb53b

comparison

equal deleted inserted replaced

-:d4d919ebc31c
+:bf8f52662dc3
 "packssdw %%mm4, %%mm4                  \n\t"
 "movd %%mm0, %0                         \n\t"
 "movd %%mm4, %1                         \n\t"
 : "=r" (numEq), "=r" (dcOk)
-: "r" (src), "r" ((long)stride), "m" (c->pQPb)
+: "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
 : "%"REG_a
 );
 numEq= (-numEq) &0xFF;
 if(numEq > c->ppMode.flatnessThreshold){
 PAVGB(%%mm0, %%mm5)                           //    112246        /16
 "movq %%mm5, (%%"REG_a", %1, 4)         \n\t" //        X
 "sub %1, %0                             \n\t"
 :
-: "r" (src), "r" ((long)stride), "m" (c->pQPb)
+: "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
 : "%"REG_a, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 const int l1= stride;
 const int l2= stride + l1;
 "psubsb %%mm5, %%mm2                    \n\t"
 "psubb %%mm6, %%mm2                     \n\t"
 "movq %%mm2, (%%"REG_c", %1)            \n\t"
 :
-: "r" (src), "r" ((long)stride)
+: "r" (src), "r" ((x86_reg)stride)
 : "%"REG_a, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 const int l1= stride;
 const int l2= stride + l1;
 "paddusb %%mm1, %%mm0                   \n\t"
 "pxor %%mm2, %%mm0                      \n\t"
 "movq %%mm0, (%%"REG_c", %1, 2)         \n\t" // line 7
 :
-: "r" (src), "r" ((long)stride), "m" (co->pQPb)
+: "r" (src), "r" ((x86_reg)stride), "m" (co->pQPb)
 : "%"REG_a, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 const int l1= stride;
 "pxor %%mm1, %%mm2                      \n\t"
 "movq %%mm0, (%%"REG_a", %1, 2)         \n\t"
 "movq %%mm2, (%0, %1, 4)                \n\t"
 :
-: "r" (src), "r" ((long)stride), "m" (c->pQPb)
+: "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb)
 : "%"REG_a, "%"REG_c
 );
 /*
 {
 "movq (%0, %1), %%mm0                   \n\t"
 "psubb %%mm4, %%mm0                     \n\t"
 "movq %%mm0, (%0, %1)                   \n\t"
 : "+r" (src)
-: "r" ((long)stride), "m" (c->pQPb)
+: "r" ((x86_reg)stride), "m" (c->pQPb)
 : "%"REG_a, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 const int l1= stride;
 const int l2= stride + l1;
 DERING_CORE((%%REGd, %1)   ,(%%REGd, %1, 2),%%mm4,%%mm0,%%mm2,%%mm5,%%mm1,%%mm3,%%mm6,%%mm7)
 DERING_CORE((%%REGd, %1, 2),(%0, %1, 8)    ,%%mm0,%%mm2,%%mm4,%%mm1,%%mm3,%%mm5,%%mm6,%%mm7)
 DERING_CORE((%0, %1, 8)    ,(%%REGd, %1, 4),%%mm2,%%mm4,%%mm0,%%mm3,%%mm5,%%mm1,%%mm6,%%mm7)
 "1:                        \n\t"
-: : "r" (src), "r" ((long)stride), "m" (c->pQPb), "m"(c->pQPb2)
+: : "r" (src), "r" ((x86_reg)stride), "m" (c->pQPb), "m"(c->pQPb2)
 : "%"REG_a, "%"REG_d, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 int y;
 int min=255;
 "movq %%mm0, (%%"REG_c")                \n\t"
 "movq (%0, %1, 8), %%mm0                \n\t"
 PAVGB(%%mm0, %%mm1)
 "movq %%mm1, (%%"REG_c", %1, 2)         \n\t"
-: : "r" (src), "r" ((long)stride)
+: : "r" (src), "r" ((x86_reg)stride)
 : "%"REG_a, "%"REG_c
 );
 #else
 int a, b, x;
 src+= 4*stride;
 DEINT_CUBIC((%0)        , (%%REGa, %1), (%%REGa, %1, 2), (%0, %1, 4) , (%%REGd, %1))
 DEINT_CUBIC((%%REGa, %1), (%0, %1, 4) , (%%REGd)       , (%%REGd, %1), (%0, %1, 8))
 DEINT_CUBIC((%0, %1, 4) , (%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8) , (%%REGc))
 DEINT_CUBIC((%%REGd, %1), (%0, %1, 8) , (%%REGd, %1, 4), (%%REGc)    , (%%REGc, %1, 2))
-: : "r" (src), "r" ((long)stride)
+: : "r" (src), "r" ((x86_reg)stride)
 : "%"REG_a, "%"REG_d, "%"REG_c
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 int x;
 src+= stride*3;
 DEINT_FF((%%REGa, %1), (%%REGa, %1, 2), (%0, %1, 4) , (%%REGd)       )
 DEINT_FF((%0, %1, 4) , (%%REGd)       , (%%REGd, %1), (%%REGd, %1, 2))
 DEINT_FF((%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8) , (%%REGd, %1, 4))
 "movq %%mm0, (%2)                       \n\t"
-: : "r" (src), "r" ((long)stride), "r"(tmp)
+: : "r" (src), "r" ((x86_reg)stride), "r"(tmp)
 : "%"REG_a, "%"REG_d
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 int x;
 src+= stride*4;
 DEINT_L5(%%mm0, %%mm1, (%%REGd, %1)   , (%%REGd, %1, 2), (%0, %1, 8)   )
 DEINT_L5(%%mm1, %%mm0, (%%REGd, %1, 2), (%0, %1, 8)    , (%%REGd, %1, 4))
 "movq %%mm0, (%2)                       \n\t"
 "movq %%mm1, (%3)                       \n\t"
-: : "r" (src), "r" ((long)stride), "r"(tmp), "r"(tmp2)
+: : "r" (src), "r" ((x86_reg)stride), "r"(tmp), "r"(tmp2)
 : "%"REG_a, "%"REG_d
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 int x;
 src+= stride*4;
 PAVGB(%%mm0, %%mm2)                           // L7+L9
 PAVGB(%%mm1, %%mm2)                           // 2L8 + L7 + L9
 "movq %%mm2, (%%"REG_d", %1, 2)         \n\t"
 "movq %%mm1, (%2)                       \n\t"
-: : "r" (src), "r" ((long)stride), "r" (tmp)
+: : "r" (src), "r" ((x86_reg)stride), "r" (tmp)
 : "%"REG_a, "%"REG_d
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 int a, b, c, x;
 src+= 4*stride;
 "pmaxub %%mm1, %%mm0                    \n\t" //
 "pminub %%mm0, %%mm2                    \n\t"
 "movq %%mm2, (%%"REG_d", %1, 2)         \n\t"
-: : "r" (src), "r" ((long)stride)
+: : "r" (src), "r" ((x86_reg)stride)
 : "%"REG_a, "%"REG_d
 );
 #else // MMX without MMX2
 __asm__ volatile(
 MEDIAN((%0)        , (%%REGa)       , (%%REGa, %1))
 MEDIAN((%%REGa, %1), (%%REGa, %1, 2), (%0, %1, 4))
 MEDIAN((%0, %1, 4) , (%%REGd)       , (%%REGd, %1))
 MEDIAN((%%REGd, %1), (%%REGd, %1, 2), (%0, %1, 8))
-: : "r" (src), "r" ((long)stride)
+: : "r" (src), "r" ((x86_reg)stride)
 : "%"REG_a, "%"REG_d
 );
 #endif //HAVE_MMX2
 #else //HAVE_MMX
 int x, y;
 "movd %%mm1, 100(%3)                    \n\t"
 "psrlq $32, %%mm1                       \n\t"
 "movd %%mm1, 116(%3)                    \n\t"
-:: "r" (src), "r" ((long)srcStride), "r" (dst1), "r" (dst2)
+:: "r" (src), "r" ((x86_reg)srcStride), "r" (dst1), "r" (dst2)
 : "%"REG_a
 );
 }
 /**
 "movd %%mm2, 4(%%"REG_d")               \n\t"
 "movd %%mm1, 4(%%"REG_d", %1)           \n\t"
 "psrlq $32, %%mm1                       \n\t"
 "movd %%mm1, 4(%%"REG_d", %1, 2)        \n\t"
-:: "r" (dst), "r" ((long)dstStride), "r" (src)
+:: "r" (dst), "r" ((x86_reg)dstStride), "r" (src)
 : "%"REG_a, "%"REG_d
 );
 }
 #endif //HAVE_MMX
 //static long test=0;
 "movq %%mm2, (%0, %%"REG_a", 2)         \n\t" // L6
 "movq %%mm3, (%0, %%"REG_c")            \n\t" // L7
 "4:                                     \n\t"
-:: "r" (src), "r" (tempBlurred), "r"((long)stride), "m" (tempBlurredPast)
+:: "r" (src), "r" (tempBlurred), "r"((x86_reg)stride), "m" (tempBlurredPast)
 : "%"REG_a, "%"REG_d, "%"REG_c, "memory"
 );
 #else //defined (HAVE_MMX2) || defined (HAVE_3DNOW)
 {
 int y;
 "psubb %%mm0, %%mm6                     \n\t"
 "pcmpgtb %%mm7, %%mm6                   \n\t"
 "movq %%mm6, %0                         \n\t"
 : "=m" (eq_mask), "=m" (dc_mask)
-: "r" (src), "r" ((long)step), "m" (c->pQPb), "m"(c->ppMode.flatnessThreshold)
+: "r" (src), "r" ((x86_reg)step), "m" (c->pQPb), "m"(c->ppMode.flatnessThreshold)
 : "%"REG_a
 );
 both_masks = dc_mask & eq_mask;
 if(both_masks){
-long offset= -8*step;
+x86_reg offset= -8*step;
 int64_t *temp_sums= sums;
 __asm__ volatile(
 "movq %2, %%mm0                         \n\t"  // QP,..., QP
 "pxor %%mm4, %%mm4                      \n\t"
 "movq %%mm1, 152(%3)                    \n\t"
 "mov %4, %0                             \n\t" //FIXME
 : "+&r"(src)
-: "r" ((long)step), "m" (c->pQPb), "r"(sums), "g"(src)
+: "r" ((x86_reg)step), "m" (c->pQPb), "r"(sums), "g"(src)
 );
 src+= step; // src points to begin of the 8x8 Block
 __asm__ volatile(
 "add $16, %1                            \n\t"
 "add %2, %0                             \n\t"
 " js 1b                                 \n\t"
 : "+r"(offset), "+r"(temp_sums)
-: "r" ((long)step), "r"(src - offset), "m"(both_masks)
+: "r" ((x86_reg)step), "r"(src - offset), "m"(both_masks)
 );
 }else
 src+= step; // src points to begin of the 8x8 Block
 if(eq_mask != -1LL){
 "movq (%0, %1), %%mm0                   \n\t"
 "psubb %%mm1, %%mm0                     \n\t"
 "movq %%mm0, (%0, %1)                   \n\t"
 : "+r" (temp_src)
-: "r" ((long)step), "m" (c->pQPb), "m"(eq_mask)
+: "r" ((x86_reg)step), "m" (c->pQPb), "m"(eq_mask)
 : "%"REG_a, "%"REG_c
 );
 }
 /*if(step==16){
 STOP_TIMER("step16")
 : "=&a" (packedOffsetAndScale)
 : "0" (packedOffsetAndScale),
 "r"(src),
 "r"(dst),
-"r" ((long)srcStride),
+"r" ((x86_reg)srcStride),
-"r" ((long)dstStride)
+"r" ((x86_reg)dstStride)
 : "%"REG_d
 );
 #else //HAVE_MMX
 for(i=0; i<8; i++)
 memcpy( &(dst[dstStride*i]),
 "lea (%%"REG_d",%3,4), %%"REG_d"        \n\t"
 SIMPLE_CPY((%%REGa, %2), (%%REGa, %2, 2), (%%REGd, %3), (%%REGd, %3, 2))
 : : "r" (src),
 "r" (dst),
-"r" ((long)srcStride),
+"r" ((x86_reg)srcStride),
-"r" ((long)dstStride)
+"r" ((x86_reg)dstStride)
 : "%"REG_a, "%"REG_d
 );
 #else //HAVE_MMX
 for(i=0; i<8; i++)
 memcpy( &(dst[dstStride*i]),
 "add %1, %0                     \n\t"
 "movq %%mm0, (%0)               \n\t"
 "movq %%mm0, (%0, %1)           \n\t"
 "movq %%mm0, (%0, %1, 2)        \n\t"
 : "+r" (src)
-: "r" ((long)-stride)
+: "r" ((x86_reg)-stride)
 );
 #else
 int i;
 uint8_t *p=src;
 for(i=0; i<3; i++){
 "prefetcht0 32(%%"REG_d", %2)   \n\t"
 "add %1, %%"REG_a"              \n\t"
 "add %3, %%"REG_d"              \n\t"
 "prefetchnta 32(%%"REG_a", %0)  \n\t"
 "prefetcht0 32(%%"REG_d", %2)   \n\t"
-:: "r" (srcBlock), "r" ((long)srcStride), "r" (dstBlock), "r" ((long)dstStride),
+:: "r" (srcBlock), "r" ((x86_reg)srcStride), "r" (dstBlock), "r" ((x86_reg)dstStride),
-"g" ((long)x), "g" ((long)copyAhead)
+"g" ((x86_reg)x), "g" ((x86_reg)copyAhead)
 : "%"REG_a, "%"REG_d
 );
 #elif defined(HAVE_3DNOW)
 //FIXME check if this is faster on an 3dnow chip or if it is faster without the prefetch or ...
 "prefetcht0 32(%%"REG_d", %2)   \n\t"
 "add %1, %%"REG_a"              \n\t"
 "add %3, %%"REG_d"              \n\t"
 "prefetchnta 32(%%"REG_a", %0)  \n\t"
 "prefetcht0 32(%%"REG_d", %2)   \n\t"
-:: "r" (srcBlock), "r" ((long)srcStride), "r" (dstBlock), "r" ((long)dstStride),
+:: "r" (srcBlock), "r" ((x86_reg)srcStride), "r" (dstBlock), "r" ((x86_reg)dstStride),
-"g" ((long)x), "g" ((long)copyAhead)
+"g" ((x86_reg)x), "g" ((x86_reg)copyAhead)
 : "%"REG_a, "%"REG_d
 );
 #elif defined(HAVE_3DNOW)
 //FIXME check if this is faster on an 3dnow chip or if it is faster without the prefetch or ...

Mercurial > libpostproc.hg

comparison postprocess_template.c @ 113:bf8f52662dc3 libpostproc