Mercurial > libavcodec.hg
comparison sparc/vis.h @ 8031:eebc7209c47f libavcodec
Convert asm keyword into __asm__.
Neither the asm() nor the __asm__() keyword is part of the C99
standard, but while GCC accepts the former in C89 syntax, it is not
accepted in C99 unless GNU extensions are turned on (with -fasm). The
latter form is accepted in any syntax as an extension (without
requiring further command-line options).
Sun Studio C99 compiler also does not accept asm() while accepting
__asm__(), albeit reporting warnings that it's not valid C99 syntax.
| author | flameeyes |
|---|---|
| date | Thu, 16 Oct 2008 13:34:09 +0000 |
| parents | c4a4495715dd |
| children | f9c847fb4839 |
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| 8030:a512ac8fa540 | 8031:eebc7209c47f |
|---|---|
| 53 #define vis_rs2_d(X) (vis_dreg(X) << 0) | 53 #define vis_rs2_d(X) (vis_dreg(X) << 0) |
| 54 #define vis_rd_s(X) (vis_sreg(X) << 25) | 54 #define vis_rd_s(X) (vis_sreg(X) << 25) |
| 55 #define vis_rd_d(X) (vis_dreg(X) << 25) | 55 #define vis_rd_d(X) (vis_dreg(X) << 25) |
| 56 | 56 |
| 57 #define vis_ss2s(opf,rs1,rs2,rd) \ | 57 #define vis_ss2s(opf,rs1,rs2,rd) \ |
| 58 asm volatile (".word %0" \ | 58 __asm__ volatile (".word %0" \ |
| 59 : : "i" (vis_opc_base | vis_opf(opf) | \ | 59 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 60 vis_rs1_s(rs1) | \ | 60 vis_rs1_s(rs1) | \ |
| 61 vis_rs2_s(rs2) | \ | 61 vis_rs2_s(rs2) | \ |
| 62 vis_rd_s(rd))) | 62 vis_rd_s(rd))) |
| 63 | 63 |
| 64 #define vis_dd2d(opf,rs1,rs2,rd) \ | 64 #define vis_dd2d(opf,rs1,rs2,rd) \ |
| 65 asm volatile (".word %0" \ | 65 __asm__ volatile (".word %0" \ |
| 66 : : "i" (vis_opc_base | vis_opf(opf) | \ | 66 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 67 vis_rs1_d(rs1) | \ | 67 vis_rs1_d(rs1) | \ |
| 68 vis_rs2_d(rs2) | \ | 68 vis_rs2_d(rs2) | \ |
| 69 vis_rd_d(rd))) | 69 vis_rd_d(rd))) |
| 70 | 70 |
| 71 #define vis_ss2d(opf,rs1,rs2,rd) \ | 71 #define vis_ss2d(opf,rs1,rs2,rd) \ |
| 72 asm volatile (".word %0" \ | 72 __asm__ volatile (".word %0" \ |
| 73 : : "i" (vis_opc_base | vis_opf(opf) | \ | 73 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 74 vis_rs1_s(rs1) | \ | 74 vis_rs1_s(rs1) | \ |
| 75 vis_rs2_s(rs2) | \ | 75 vis_rs2_s(rs2) | \ |
| 76 vis_rd_d(rd))) | 76 vis_rd_d(rd))) |
| 77 | 77 |
| 78 #define vis_sd2d(opf,rs1,rs2,rd) \ | 78 #define vis_sd2d(opf,rs1,rs2,rd) \ |
| 79 asm volatile (".word %0" \ | 79 __asm__ volatile (".word %0" \ |
| 80 : : "i" (vis_opc_base | vis_opf(opf) | \ | 80 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 81 vis_rs1_s(rs1) | \ | 81 vis_rs1_s(rs1) | \ |
| 82 vis_rs2_d(rs2) | \ | 82 vis_rs2_d(rs2) | \ |
| 83 vis_rd_d(rd))) | 83 vis_rd_d(rd))) |
| 84 | 84 |
| 85 #define vis_d2s(opf,rs2,rd) \ | 85 #define vis_d2s(opf,rs2,rd) \ |
| 86 asm volatile (".word %0" \ | 86 __asm__ volatile (".word %0" \ |
| 87 : : "i" (vis_opc_base | vis_opf(opf) | \ | 87 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 88 vis_rs2_d(rs2) | \ | 88 vis_rs2_d(rs2) | \ |
| 89 vis_rd_s(rd))) | 89 vis_rd_s(rd))) |
| 90 | 90 |
| 91 #define vis_s2d(opf,rs2,rd) \ | 91 #define vis_s2d(opf,rs2,rd) \ |
| 92 asm volatile (".word %0" \ | 92 __asm__ volatile (".word %0" \ |
| 93 : : "i" (vis_opc_base | vis_opf(opf) | \ | 93 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 94 vis_rs2_s(rs2) | \ | 94 vis_rs2_s(rs2) | \ |
| 95 vis_rd_d(rd))) | 95 vis_rd_d(rd))) |
| 96 | 96 |
| 97 #define vis_d12d(opf,rs1,rd) \ | 97 #define vis_d12d(opf,rs1,rd) \ |
| 98 asm volatile (".word %0" \ | 98 __asm__ volatile (".word %0" \ |
| 99 : : "i" (vis_opc_base | vis_opf(opf) | \ | 99 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 100 vis_rs1_d(rs1) | \ | 100 vis_rs1_d(rs1) | \ |
| 101 vis_rd_d(rd))) | 101 vis_rd_d(rd))) |
| 102 | 102 |
| 103 #define vis_d22d(opf,rs2,rd) \ | 103 #define vis_d22d(opf,rs2,rd) \ |
| 104 asm volatile (".word %0" \ | 104 __asm__ volatile (".word %0" \ |
| 105 : : "i" (vis_opc_base | vis_opf(opf) | \ | 105 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 106 vis_rs2_d(rs2) | \ | 106 vis_rs2_d(rs2) | \ |
| 107 vis_rd_d(rd))) | 107 vis_rd_d(rd))) |
| 108 | 108 |
| 109 #define vis_s12s(opf,rs1,rd) \ | 109 #define vis_s12s(opf,rs1,rd) \ |
| 110 asm volatile (".word %0" \ | 110 __asm__ volatile (".word %0" \ |
| 111 : : "i" (vis_opc_base | vis_opf(opf) | \ | 111 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 112 vis_rs1_s(rs1) | \ | 112 vis_rs1_s(rs1) | \ |
| 113 vis_rd_s(rd))) | 113 vis_rd_s(rd))) |
| 114 | 114 |
| 115 #define vis_s22s(opf,rs2,rd) \ | 115 #define vis_s22s(opf,rs2,rd) \ |
| 116 asm volatile (".word %0" \ | 116 __asm__ volatile (".word %0" \ |
| 117 : : "i" (vis_opc_base | vis_opf(opf) | \ | 117 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 118 vis_rs2_s(rs2) | \ | 118 vis_rs2_s(rs2) | \ |
| 119 vis_rd_s(rd))) | 119 vis_rd_s(rd))) |
| 120 | 120 |
| 121 #define vis_s(opf,rd) \ | 121 #define vis_s(opf,rd) \ |
| 122 asm volatile (".word %0" \ | 122 __asm__ volatile (".word %0" \ |
| 123 : : "i" (vis_opc_base | vis_opf(opf) | \ | 123 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 124 vis_rd_s(rd))) | 124 vis_rd_s(rd))) |
| 125 | 125 |
| 126 #define vis_d(opf,rd) \ | 126 #define vis_d(opf,rd) \ |
| 127 asm volatile (".word %0" \ | 127 __asm__ volatile (".word %0" \ |
| 128 : : "i" (vis_opc_base | vis_opf(opf) | \ | 128 : : "i" (vis_opc_base | vis_opf(opf) | \ |
| 129 vis_rd_d(rd))) | 129 vis_rd_d(rd))) |
| 130 | 130 |
| 131 #define vis_r2m(op,rd,mem) \ | 131 #define vis_r2m(op,rd,mem) \ |
| 132 asm volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) | 132 __asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) |
| 133 | 133 |
| 134 #define vis_r2m_2(op,rd,mem1,mem2) \ | 134 #define vis_r2m_2(op,rd,mem1,mem2) \ |
| 135 asm volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) | 135 __asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) |
| 136 | 136 |
| 137 #define vis_m2r(op,mem,rd) \ | 137 #define vis_m2r(op,mem,rd) \ |
| 138 asm volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) | 138 __asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) |
| 139 | 139 |
| 140 #define vis_m2r_2(op,mem1,mem2,rd) \ | 140 #define vis_m2r_2(op,mem1,mem2,rd) \ |
| 141 asm volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) | 141 __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) |
| 142 | 142 |
| 143 static inline void vis_set_gsr(unsigned int _val) | 143 static inline void vis_set_gsr(unsigned int _val) |
| 144 { | 144 { |
| 145 register unsigned int val asm("g1"); | 145 register unsigned int val __asm__("g1"); |
| 146 | 146 |
| 147 val = _val; | 147 val = _val; |
| 148 asm volatile(".word 0xa7804000" | 148 __asm__ volatile(".word 0xa7804000" |
| 149 : : "r" (val)); | 149 : : "r" (val)); |
| 150 } | 150 } |
| 151 | 151 |
| 152 #define VIS_GSR_ALIGNADDR_MASK 0x0000007 | 152 #define VIS_GSR_ALIGNADDR_MASK 0x0000007 |
| 153 #define VIS_GSR_ALIGNADDR_SHIFT 0 | 153 #define VIS_GSR_ALIGNADDR_SHIFT 0 |
| 162 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) | 162 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) |
| 163 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) | 163 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) |
| 164 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) | 164 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) |
| 165 | 165 |
| 166 #define vis_ldblk(mem, rd) \ | 166 #define vis_ldblk(mem, rd) \ |
| 167 do { register void *__mem asm("g1"); \ | 167 do { register void *__mem __asm__("g1"); \ |
| 168 __mem = &(mem); \ | 168 __mem = &(mem); \ |
| 169 asm volatile(".word 0xc1985e00 | %1" \ | 169 __asm__ volatile(".word 0xc1985e00 | %1" \ |
| 170 : \ | 170 : \ |
| 171 : "r" (__mem), \ | 171 : "r" (__mem), \ |
| 172 "i" (vis_rd_d(rd)) \ | 172 "i" (vis_rd_d(rd)) \ |
| 173 : "memory"); \ | 173 : "memory"); \ |
| 174 } while (0) | 174 } while (0) |
| 175 | 175 |
| 176 #define vis_stblk(rd, mem) \ | 176 #define vis_stblk(rd, mem) \ |
| 177 do { register void *__mem asm("g1"); \ | 177 do { register void *__mem __asm__("g1"); \ |
| 178 __mem = &(mem); \ | 178 __mem = &(mem); \ |
| 179 asm volatile(".word 0xc1b85e00 | %1" \ | 179 __asm__ volatile(".word 0xc1b85e00 | %1" \ |
| 180 : \ | 180 : \ |
| 181 : "r" (__mem), \ | 181 : "r" (__mem), \ |
| 182 "i" (vis_rd_d(rd)) \ | 182 "i" (vis_rd_d(rd)) \ |
| 183 : "memory"); \ | 183 : "memory"); \ |
| 184 } while (0) | 184 } while (0) |
| 185 | 185 |
| 186 #define vis_membar_storestore() \ | 186 #define vis_membar_storestore() \ |
| 187 asm volatile(".word 0x8143e008" : : : "memory") | 187 __asm__ volatile(".word 0x8143e008" : : : "memory") |
| 188 | 188 |
| 189 #define vis_membar_sync() \ | 189 #define vis_membar_sync() \ |
| 190 asm volatile(".word 0x8143e040" : : : "memory") | 190 __asm__ volatile(".word 0x8143e040" : : : "memory") |
| 191 | 191 |
| 192 /* 16 and 32 bit partitioned addition and subtraction. The normal | 192 /* 16 and 32 bit partitioned addition and subtraction. The normal |
| 193 * versions perform 4 16-bit or 2 32-bit additions or subtractions. | 193 * versions perform 4 16-bit or 2 32-bit additions or subtractions. |
| 194 * The 's' versions perform 2 16-bit or 1 32-bit additions or | 194 * The 's' versions perform 2 16-bit or 1 32-bit additions or |
| 195 * subtractions. | 195 * subtractions. |
| 224 | 224 |
| 225 /* Alignment instructions. */ | 225 /* Alignment instructions. */ |
| 226 | 226 |
| 227 static inline void *vis_alignaddr(void *_ptr) | 227 static inline void *vis_alignaddr(void *_ptr) |
| 228 { | 228 { |
| 229 register void *ptr asm("g1"); | 229 register void *ptr __asm__("g1"); |
| 230 | 230 |
| 231 ptr = _ptr; | 231 ptr = _ptr; |
| 232 | 232 |
| 233 asm volatile(".word %2" | 233 __asm__ volatile(".word %2" |
| 234 : "=&r" (ptr) | 234 : "=&r" (ptr) |
| 235 : "0" (ptr), | 235 : "0" (ptr), |
| 236 "i" (vis_opc_base | vis_opf(0x18) | | 236 "i" (vis_opc_base | vis_opf(0x18) | |
| 237 vis_rs1_s(1) | | 237 vis_rs1_s(1) | |
| 238 vis_rs2_s(0) | | 238 vis_rs2_s(0) | |
| 241 return ptr; | 241 return ptr; |
| 242 } | 242 } |
| 243 | 243 |
| 244 static inline void vis_alignaddr_g0(void *_ptr) | 244 static inline void vis_alignaddr_g0(void *_ptr) |
| 245 { | 245 { |
| 246 register void *ptr asm("g1"); | 246 register void *ptr __asm__("g1"); |
| 247 | 247 |
| 248 ptr = _ptr; | 248 ptr = _ptr; |
| 249 | 249 |
| 250 asm volatile(".word %2" | 250 __asm__ volatile(".word %2" |
| 251 : "=&r" (ptr) | 251 : "=&r" (ptr) |
| 252 : "0" (ptr), | 252 : "0" (ptr), |
| 253 "i" (vis_opc_base | vis_opf(0x18) | | 253 "i" (vis_opc_base | vis_opf(0x18) | |
| 254 vis_rs1_s(1) | | 254 vis_rs1_s(1) | |
| 255 vis_rs2_s(0) | | 255 vis_rs2_s(0) | |
| 256 vis_rd_s(0))); | 256 vis_rd_s(0))); |
| 257 } | 257 } |
| 258 | 258 |
| 259 static inline void *vis_alignaddrl(void *_ptr) | 259 static inline void *vis_alignaddrl(void *_ptr) |
| 260 { | 260 { |
| 261 register void *ptr asm("g1"); | 261 register void *ptr __asm__("g1"); |
| 262 | 262 |
| 263 ptr = _ptr; | 263 ptr = _ptr; |
| 264 | 264 |
| 265 asm volatile(".word %2" | 265 __asm__ volatile(".word %2" |
| 266 : "=&r" (ptr) | 266 : "=&r" (ptr) |
| 267 : "0" (ptr), | 267 : "0" (ptr), |
| 268 "i" (vis_opc_base | vis_opf(0x19) | | 268 "i" (vis_opc_base | vis_opf(0x19) | |
| 269 vis_rs1_s(1) | | 269 vis_rs1_s(1) | |
| 270 vis_rs2_s(0) | | 270 vis_rs2_s(0) | |
| 273 return ptr; | 273 return ptr; |
| 274 } | 274 } |
| 275 | 275 |
| 276 static inline void vis_alignaddrl_g0(void *_ptr) | 276 static inline void vis_alignaddrl_g0(void *_ptr) |
| 277 { | 277 { |
| 278 register void *ptr asm("g1"); | 278 register void *ptr __asm__("g1"); |
| 279 | 279 |
| 280 ptr = _ptr; | 280 ptr = _ptr; |
| 281 | 281 |
| 282 asm volatile(".word %2" | 282 __asm__ volatile(".word %2" |
| 283 : "=&r" (ptr) | 283 : "=&r" (ptr) |
| 284 : "0" (ptr), | 284 : "0" (ptr), |
| 285 "i" (vis_opc_base | vis_opf(0x19) | | 285 "i" (vis_opc_base | vis_opf(0x19) | |
| 286 vis_rs1_s(1) | | 286 vis_rs1_s(1) | |
| 287 vis_rs2_s(0) | | 287 vis_rs2_s(0) | |