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comparison sparc/vis.h @ 2979:bfabfdf9ce55 libavcodec

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author diego
date Thu, 22 Dec 2005 01:10:11 +0000
parents 55b7435c59b8
children 0b546eab515d
comparison
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2978:403183bbb505 2979:bfabfdf9ce55
39 * 39 *
40 * Thus, we do the opcode encoding by hand and output 32-bit words in 40 * Thus, we do the opcode encoding by hand and output 32-bit words in
41 * the assembler to keep the binary from becoming tainted. 41 * the assembler to keep the binary from becoming tainted.
42 */ 42 */
43 43
44 #define vis_opc_base ((0x1 << 31) | (0x36 << 19)) 44 #define vis_opc_base ((0x1 << 31) | (0x36 << 19))
45 #define vis_opf(X) ((X) << 5) 45 #define vis_opf(X) ((X) << 5)
46 #define vis_sreg(X) (X) 46 #define vis_sreg(X) (X)
47 #define vis_dreg(X) (((X)&0x1f)|((X)>>5)) 47 #define vis_dreg(X) (((X)&0x1f)|((X)>>5))
48 #define vis_rs1_s(X) (vis_sreg(X) << 14) 48 #define vis_rs1_s(X) (vis_sreg(X) << 14)
49 #define vis_rs1_d(X) (vis_dreg(X) << 14) 49 #define vis_rs1_d(X) (vis_dreg(X) << 14)
50 #define vis_rs2_s(X) (vis_sreg(X) << 0) 50 #define vis_rs2_s(X) (vis_sreg(X) << 0)
51 #define vis_rs2_d(X) (vis_dreg(X) << 0) 51 #define vis_rs2_d(X) (vis_dreg(X) << 0)
52 #define vis_rd_s(X) (vis_sreg(X) << 25) 52 #define vis_rd_s(X) (vis_sreg(X) << 25)
53 #define vis_rd_d(X) (vis_dreg(X) << 25) 53 #define vis_rd_d(X) (vis_dreg(X) << 25)
54 54
55 #define vis_ss2s(opf,rs1,rs2,rd) \ 55 #define vis_ss2s(opf,rs1,rs2,rd) \
56 __asm__ __volatile__ (".word %0" \ 56 __asm__ __volatile__ (".word %0" \
57 : : "i" (vis_opc_base | vis_opf(opf) | \ 57 : : "i" (vis_opc_base | vis_opf(opf) | \
58 vis_rs1_s(rs1) | \ 58 vis_rs1_s(rs1) | \
59 vis_rs2_s(rs2) | \ 59 vis_rs2_s(rs2) | \
60 vis_rd_s(rd))) 60 vis_rd_s(rd)))
61 61
62 #define vis_dd2d(opf,rs1,rs2,rd) \ 62 #define vis_dd2d(opf,rs1,rs2,rd) \
63 __asm__ __volatile__ (".word %0" \ 63 __asm__ __volatile__ (".word %0" \
64 : : "i" (vis_opc_base | vis_opf(opf) | \ 64 : : "i" (vis_opc_base | vis_opf(opf) | \
65 vis_rs1_d(rs1) | \ 65 vis_rs1_d(rs1) | \
66 vis_rs2_d(rs2) | \ 66 vis_rs2_d(rs2) | \
67 vis_rd_d(rd))) 67 vis_rd_d(rd)))
68 68
69 #define vis_ss2d(opf,rs1,rs2,rd) \ 69 #define vis_ss2d(opf,rs1,rs2,rd) \
70 __asm__ __volatile__ (".word %0" \ 70 __asm__ __volatile__ (".word %0" \
71 : : "i" (vis_opc_base | vis_opf(opf) | \ 71 : : "i" (vis_opc_base | vis_opf(opf) | \
72 vis_rs1_s(rs1) | \ 72 vis_rs1_s(rs1) | \
73 vis_rs2_s(rs2) | \ 73 vis_rs2_s(rs2) | \
74 vis_rd_d(rd))) 74 vis_rd_d(rd)))
75 75
76 #define vis_sd2d(opf,rs1,rs2,rd) \ 76 #define vis_sd2d(opf,rs1,rs2,rd) \
77 __asm__ __volatile__ (".word %0" \ 77 __asm__ __volatile__ (".word %0" \
78 : : "i" (vis_opc_base | vis_opf(opf) | \ 78 : : "i" (vis_opc_base | vis_opf(opf) | \
79 vis_rs1_s(rs1) | \ 79 vis_rs1_s(rs1) | \
80 vis_rs2_d(rs2) | \ 80 vis_rs2_d(rs2) | \
81 vis_rd_d(rd))) 81 vis_rd_d(rd)))
82 82
83 #define vis_d2s(opf,rs2,rd) \ 83 #define vis_d2s(opf,rs2,rd) \
84 __asm__ __volatile__ (".word %0" \ 84 __asm__ __volatile__ (".word %0" \
85 : : "i" (vis_opc_base | vis_opf(opf) | \ 85 : : "i" (vis_opc_base | vis_opf(opf) | \
86 vis_rs2_d(rs2) | \ 86 vis_rs2_d(rs2) | \
87 vis_rd_s(rd))) 87 vis_rd_s(rd)))
88 88
89 #define vis_s2d(opf,rs2,rd) \ 89 #define vis_s2d(opf,rs2,rd) \
90 __asm__ __volatile__ (".word %0" \ 90 __asm__ __volatile__ (".word %0" \
91 : : "i" (vis_opc_base | vis_opf(opf) | \ 91 : : "i" (vis_opc_base | vis_opf(opf) | \
92 vis_rs2_s(rs2) | \ 92 vis_rs2_s(rs2) | \
93 vis_rd_d(rd))) 93 vis_rd_d(rd)))
94 94
95 #define vis_d12d(opf,rs1,rd) \ 95 #define vis_d12d(opf,rs1,rd) \
96 __asm__ __volatile__ (".word %0" \ 96 __asm__ __volatile__ (".word %0" \
97 : : "i" (vis_opc_base | vis_opf(opf) | \ 97 : : "i" (vis_opc_base | vis_opf(opf) | \
98 vis_rs1_d(rs1) | \ 98 vis_rs1_d(rs1) | \
99 vis_rd_d(rd))) 99 vis_rd_d(rd)))
100 100
101 #define vis_d22d(opf,rs2,rd) \ 101 #define vis_d22d(opf,rs2,rd) \
102 __asm__ __volatile__ (".word %0" \ 102 __asm__ __volatile__ (".word %0" \
103 : : "i" (vis_opc_base | vis_opf(opf) | \ 103 : : "i" (vis_opc_base | vis_opf(opf) | \
104 vis_rs2_d(rs2) | \ 104 vis_rs2_d(rs2) | \
105 vis_rd_d(rd))) 105 vis_rd_d(rd)))
106 106
107 #define vis_s12s(opf,rs1,rd) \ 107 #define vis_s12s(opf,rs1,rd) \
108 __asm__ __volatile__ (".word %0" \ 108 __asm__ __volatile__ (".word %0" \
109 : : "i" (vis_opc_base | vis_opf(opf) | \ 109 : : "i" (vis_opc_base | vis_opf(opf) | \
110 vis_rs1_s(rs1) | \ 110 vis_rs1_s(rs1) | \
111 vis_rd_s(rd))) 111 vis_rd_s(rd)))
112 112
113 #define vis_s22s(opf,rs2,rd) \ 113 #define vis_s22s(opf,rs2,rd) \
114 __asm__ __volatile__ (".word %0" \ 114 __asm__ __volatile__ (".word %0" \
115 : : "i" (vis_opc_base | vis_opf(opf) | \ 115 : : "i" (vis_opc_base | vis_opf(opf) | \
116 vis_rs2_s(rs2) | \ 116 vis_rs2_s(rs2) | \
117 vis_rd_s(rd))) 117 vis_rd_s(rd)))
118 118
119 #define vis_s(opf,rd) \ 119 #define vis_s(opf,rd) \
120 __asm__ __volatile__ (".word %0" \ 120 __asm__ __volatile__ (".word %0" \
121 : : "i" (vis_opc_base | vis_opf(opf) | \ 121 : : "i" (vis_opc_base | vis_opf(opf) | \
122 vis_rd_s(rd))) 122 vis_rd_s(rd)))
123 123
124 #define vis_d(opf,rd) \ 124 #define vis_d(opf,rd) \
125 __asm__ __volatile__ (".word %0" \ 125 __asm__ __volatile__ (".word %0" \
126 : : "i" (vis_opc_base | vis_opf(opf) | \ 126 : : "i" (vis_opc_base | vis_opf(opf) | \
127 vis_rd_d(rd))) 127 vis_rd_d(rd)))
128 128
129 #define vis_r2m(op,rd,mem) \ 129 #define vis_r2m(op,rd,mem) \
130 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) 130 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) )
131 131
132 #define vis_r2m_2(op,rd,mem1,mem2) \ 132 #define vis_r2m_2(op,rd,mem1,mem2) \
133 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) 133 __asm__ __volatile__ (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) )
134 134
135 #define vis_m2r(op,mem,rd) \ 135 #define vis_m2r(op,mem,rd) \
136 __asm__ __volatile__ (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) 136 __asm__ __volatile__ (#op "\t[%0], %%f" #rd : : "r" (&(mem)) )
137 137
138 #define vis_m2r_2(op,mem1,mem2,rd) \ 138 #define vis_m2r_2(op,mem1,mem2,rd) \
139 __asm__ __volatile__ (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) 139 __asm__ __volatile__ (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )
140 140
141 static inline void vis_set_gsr(unsigned int _val) 141 static inline void vis_set_gsr(unsigned int _val)
142 { 142 {
143 register unsigned int val asm("g1"); 143 register unsigned int val asm("g1");
144 144
145 val = _val; 145 val = _val;
146 __asm__ __volatile__(".word 0xa7804000" 146 __asm__ __volatile__(".word 0xa7804000"
147 : : "r" (val)); 147 : : "r" (val));
148 } 148 }
149 149
150 #define VIS_GSR_ALIGNADDR_MASK 0x0000007 150 #define VIS_GSR_ALIGNADDR_MASK 0x0000007
151 #define VIS_GSR_ALIGNADDR_SHIFT 0 151 #define VIS_GSR_ALIGNADDR_SHIFT 0
152 #define VIS_GSR_SCALEFACT_MASK 0x0000078 152 #define VIS_GSR_SCALEFACT_MASK 0x0000078
153 #define VIS_GSR_SCALEFACT_SHIFT 3 153 #define VIS_GSR_SCALEFACT_SHIFT 3
154 154
155 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1) 155 #define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1)
156 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1) 156 #define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1)
157 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem) 157 #define vis_st32(rs1,mem) vis_r2m(st, rs1, mem)
158 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2) 158 #define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2)
159 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1) 159 #define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1)
160 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) 160 #define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1)
161 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) 161 #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem)
162 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) 162 #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2)
163 163
164 #define vis_ldblk(mem, rd) \ 164 #define vis_ldblk(mem, rd) \
165 do { register void *__mem asm("g1"); \ 165 do { register void *__mem asm("g1"); \
166 __mem = &(mem); \ 166 __mem = &(mem); \
167 __asm__ __volatile__(".word 0xc1985e00 | %1" \ 167 __asm__ __volatile__(".word 0xc1985e00 | %1" \
168 : \ 168 : \
169 : "r" (__mem), \ 169 : "r" (__mem), \
170 "i" (vis_rd_d(rd)) \ 170 "i" (vis_rd_d(rd)) \
171 : "memory"); \ 171 : "memory"); \
172 } while (0) 172 } while (0)
173 173
174 #define vis_stblk(rd, mem) \ 174 #define vis_stblk(rd, mem) \
175 do { register void *__mem asm("g1"); \ 175 do { register void *__mem asm("g1"); \
176 __mem = &(mem); \ 176 __mem = &(mem); \
177 __asm__ __volatile__(".word 0xc1b85e00 | %1" \ 177 __asm__ __volatile__(".word 0xc1b85e00 | %1" \
178 : \ 178 : \
179 : "r" (__mem), \ 179 : "r" (__mem), \
180 "i" (vis_rd_d(rd)) \ 180 "i" (vis_rd_d(rd)) \
181 : "memory"); \ 181 : "memory"); \
182 } while (0) 182 } while (0)
183 183
184 #define vis_membar_storestore() \ 184 #define vis_membar_storestore() \
185 __asm__ __volatile__(".word 0x8143e008" : : : "memory") 185 __asm__ __volatile__(".word 0x8143e008" : : : "memory")
186 186
187 #define vis_membar_sync() \ 187 #define vis_membar_sync() \
188 __asm__ __volatile__(".word 0x8143e040" : : : "memory") 188 __asm__ __volatile__(".word 0x8143e040" : : : "memory")
189 189
190 /* 16 and 32 bit partitioned addition and subtraction. The normal 190 /* 16 and 32 bit partitioned addition and subtraction. The normal
191 * versions perform 4 16-bit or 2 32-bit additions or subtractions. 191 * versions perform 4 16-bit or 2 32-bit additions or subtractions.
192 * The 's' versions perform 2 16-bit or 1 32-bit additions or 192 * The 's' versions perform 2 16-bit or 1 32-bit additions or
193 * subtractions. 193 * subtractions.
194 */ 194 */
195 195
196 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd) 196 #define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd)
197 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd) 197 #define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd)
198 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd) 198 #define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd)
199 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd) 199 #define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd)
200 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd) 200 #define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd)
201 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd) 201 #define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd)
202 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd) 202 #define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd)
203 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd) 203 #define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd)
204 204
205 /* Pixel formatting instructions. */ 205 /* Pixel formatting instructions. */
206 206
207 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd) 207 #define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd)
208 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd) 208 #define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd)
209 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd) 209 #define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd)
210 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd) 210 #define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd)
211 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd) 211 #define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd)
212 212
213 /* Partitioned multiply instructions. */ 213 /* Partitioned multiply instructions. */
214 214
215 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd) 215 #define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd)
216 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd) 216 #define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd)
217 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd) 217 #define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd)
218 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd) 218 #define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd)
219 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd) 219 #define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd)
220 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd) 220 #define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd)
221 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd) 221 #define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd)
222 222
223 /* Alignment instructions. */ 223 /* Alignment instructions. */
224 224
225 static inline void *vis_alignaddr(void *_ptr) 225 static inline void *vis_alignaddr(void *_ptr)
226 { 226 {
227 register void *ptr asm("g1"); 227 register void *ptr asm("g1");
228 228
229 ptr = _ptr; 229 ptr = _ptr;
230 230
231 __asm__ __volatile__(".word %2" 231 __asm__ __volatile__(".word %2"
232 : "=&r" (ptr) 232 : "=&r" (ptr)
233 : "0" (ptr), 233 : "0" (ptr),
234 "i" (vis_opc_base | vis_opf(0x18) | 234 "i" (vis_opc_base | vis_opf(0x18) |
235 vis_rs1_s(1) | 235 vis_rs1_s(1) |
236 vis_rs2_s(0) | 236 vis_rs2_s(0) |
237 vis_rd_s(1))); 237 vis_rd_s(1)));
238 238
239 return ptr; 239 return ptr;
240 } 240 }
241 241
242 static inline void vis_alignaddr_g0(void *_ptr) 242 static inline void vis_alignaddr_g0(void *_ptr)
243 { 243 {
244 register void *ptr asm("g1"); 244 register void *ptr asm("g1");
245 245
246 ptr = _ptr; 246 ptr = _ptr;
247 247
248 __asm__ __volatile__(".word %2" 248 __asm__ __volatile__(".word %2"
249 : "=&r" (ptr) 249 : "=&r" (ptr)
250 : "0" (ptr), 250 : "0" (ptr),
251 "i" (vis_opc_base | vis_opf(0x18) | 251 "i" (vis_opc_base | vis_opf(0x18) |
252 vis_rs1_s(1) | 252 vis_rs1_s(1) |
253 vis_rs2_s(0) | 253 vis_rs2_s(0) |
254 vis_rd_s(0))); 254 vis_rd_s(0)));
255 } 255 }
256 256
257 static inline void *vis_alignaddrl(void *_ptr) 257 static inline void *vis_alignaddrl(void *_ptr)
258 { 258 {
259 register void *ptr asm("g1"); 259 register void *ptr asm("g1");
260 260
261 ptr = _ptr; 261 ptr = _ptr;
262 262
263 __asm__ __volatile__(".word %2" 263 __asm__ __volatile__(".word %2"
264 : "=&r" (ptr) 264 : "=&r" (ptr)
265 : "0" (ptr), 265 : "0" (ptr),
266 "i" (vis_opc_base | vis_opf(0x19) | 266 "i" (vis_opc_base | vis_opf(0x19) |
267 vis_rs1_s(1) | 267 vis_rs1_s(1) |
268 vis_rs2_s(0) | 268 vis_rs2_s(0) |
269 vis_rd_s(1))); 269 vis_rd_s(1)));
270 270
271 return ptr; 271 return ptr;
272 } 272 }
273 273
274 static inline void vis_alignaddrl_g0(void *_ptr) 274 static inline void vis_alignaddrl_g0(void *_ptr)
275 { 275 {
276 register void *ptr asm("g1"); 276 register void *ptr asm("g1");
277 277
278 ptr = _ptr; 278 ptr = _ptr;
279 279
280 __asm__ __volatile__(".word %2" 280 __asm__ __volatile__(".word %2"
281 : "=&r" (ptr) 281 : "=&r" (ptr)
282 : "0" (ptr), 282 : "0" (ptr),
283 "i" (vis_opc_base | vis_opf(0x19) | 283 "i" (vis_opc_base | vis_opf(0x19) |
284 vis_rs1_s(1) | 284 vis_rs1_s(1) |
285 vis_rs2_s(0) | 285 vis_rs2_s(0) |
286 vis_rd_s(0))); 286 vis_rd_s(0)));
287 } 287 }
288 288
289 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) 289 #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd)
290 290
291 /* Logical operate instructions. */ 291 /* Logical operate instructions. */
292 292
293 #define vis_fzero(rd) vis_d( 0x60, rd) 293 #define vis_fzero(rd) vis_d( 0x60, rd)
294 #define vis_fzeros(rd) vis_s( 0x61, rd) 294 #define vis_fzeros(rd) vis_s( 0x61, rd)
295 #define vis_fone(rd) vis_d( 0x7e, rd) 295 #define vis_fone(rd) vis_d( 0x7e, rd)
296 #define vis_fones(rd) vis_s( 0x7f, rd) 296 #define vis_fones(rd) vis_s( 0x7f, rd)
297 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd) 297 #define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd)
298 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd) 298 #define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd)
299 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd) 299 #define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd)
300 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd) 300 #define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd)
301 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd) 301 #define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd)
302 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd) 302 #define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd)
303 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd) 303 #define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd)
304 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd) 304 #define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd)
305 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd) 305 #define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd)
306 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd) 306 #define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd)
307 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd) 307 #define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd)
308 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd) 308 #define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd)
309 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd) 309 #define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd)
310 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd) 310 #define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd)
311 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd) 311 #define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd)
312 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd) 312 #define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd)
313 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd) 313 #define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd)
314 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd) 314 #define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd)
315 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd) 315 #define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd)
316 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd) 316 #define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd)
317 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd) 317 #define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd)
318 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd) 318 #define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd)
319 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd) 319 #define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd)
320 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd) 320 #define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd)
321 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd) 321 #define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd)
322 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd) 322 #define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd)
323 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd) 323 #define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd)
324 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd) 324 #define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd)
325 325
326 /* Pixel component distance. */ 326 /* Pixel component distance. */
327 327
328 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd) 328 #define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd)